编程-交通信号灯控制问题,要改变时间

作者:用户 来源:互联网 浏览:367 次 时间:2016-09-08 16:38:12

编程交通信号灯信号灯

编程-交通信号灯控制问题,要改变时间 - 摘要: 交通信号灯控制问题,要改变时间9C交通信号灯代码,现在是灯倒数3,2,1然后在1的时候颜色转变,我想改成3,2,1,0在1之后就是0的时候变色,要怎么改代码呢?你这个有代码么,能将代码贴出来看一下么。

问题描述

交通信号灯控制问题,要改变时间

交通信号灯代码,现在是灯倒数3,2,1然后在1的时候颜色转变,我想改成3,2,1,0在1之后就是0的时候变色,要怎么改代码呢?

解决方案

你这个有代码么 ,能将代码贴出来看一下么。
应该是在代码中有一个判断逻辑,将那个判断逻辑改一下就好。

解决方案二:

让程序睡个四秒就完了

解决方案三:

要么改变寄存器的初始值,要么改变跳转条件

解决方案四:

贴上代码

  • by xmcx.
解决方案五:

新增一個燈號 0

迴圈次數多一次

應該就可以搞定了!!

還是貼上代碼比較好看怎修改!!

解决方案六:

module traf_light(
input wire clk_s, //输入的是1s的时钟信号
input clr,
input allyellow,
input allred,
output reg[5:0] lights,
output reg[8:0] timedis1, timedis2, //方向1 和方向2 的倒计时时间的初始值。
output wire pluse_1, Pluse_2 //方向1 和方向2 的倒计时 赋值脉冲,当收到对应的脉冲信号的时候,就读取对应的倒计时时间的初始值。
);

reg[2:0] state;
reg[8:0] count;
reg[8:0] time_r;

parameter s0=3'b000, s1=3'b001, s2=3'b010, //states
s3=3'b011, s4=3'b100, s5=3'b101, s6=3'b110; //s6用于显示全黄灯的状态

parameter time_g=8'd12, time_y=8'd3, time_rr=8'd2;

initial
begin
time_r <= time_g+time_y+time_rr;
state <= s0;
count <= 0;
timedis1 <= time_g;
timedis2 <= time_r;
end

always @(posedge clk_s or posedge clr)
begin
if(clr == 1)
begin
state <= s0;
count <= 0;
timedis1 <= 0;
timedis2 <= 0;
end
else
begin
if(allred == 1)
begin
state <= s5;
count <= 0;
end
else
begin
if(allyellow == 1)
begin
state <= s6;
count <= 0;
end
else
begin
case(state)
s0:if(count < time_g)
begin
state <= s0;
count <= count+1;
end
else
begin
state <= s1;
count <= 0;
timedis1 <= time_y;
end
s1:if(count < time_y)
begin
state <= s1;
count <= count+1;
end
else
begin
state <= s2;
count <= 0;
timedis1 <= time_r;
end
s2:if(count < time_rr)
begin
state <= s2;
count <= count+1;
end
else
begin
state <= s3;
count <= 0;
timedis2 <= time_g;

end
s3:if(count < time_g)
begin
state <= s3;
count <= count+1;
end
else
begin
state <= s4;
count <= 0;

timedis2 <= time_y;
end
s4:if(count < time_y)
begin
state <= s4;
count <= count+1;
end
else
begin
state <= s5;
count <= 0;
timedis2 <= time_r;
end
s5:if(count < time_rr)
begin
state <= s5;
count <= count+1;
end
else
begin
state <= s0;
count <= 0;
timedis1 <= time_g;
end
s6:begin
state <= s0;
count <= 0;
timedis1 <= time_g;

end

default state <= s2;
endcase
end
end
end
end

always @(*)
case(state)
s0: lights = 6'b001100;
s1: lights = 6'b010100;
s2: lights = 6'b100100;
s3: lights = 6'b100001;
s4: lights = 6'b100010;
s5: lights = 6'b100100;

s6: lights = 6'b010010;

default lights = 6'b100100;
endcase
endmodule
是这段吗?

解决方案七:

module traf_light(
input wire clk_s, //输入的是1s的时钟信号
input clr,
input allyellow,
input allred,
output reg[5:0] lights,
output reg[8:0] timedis1, timedis2, //方向1 和方向2 的倒计时时间的初始值。
output wire pluse_1, Pluse_2 //方向1 和方向2 的倒计时 赋值脉冲,当收到对应的脉冲信号的时候,就读取对应的倒计时时间的初始值。
);

reg[2:0] state;
reg[8:0] count;
reg[8:0] time_r;

parameter s0=3'b000, s1=3'b001, s2=3'b010, //states
s3=3'b011, s4=3'b100, s5=3'b101, s6=3'b110; //s6用于显示全黄灯的状态

parameter time_g=8'd12, time_y=8'd3, time_rr=8'd2;

initial
begin
time_r <= time_g+time_y+time_rr;
state <= s0;
count <= 0;
timedis1 <= time_g;
timedis2 <= time_r;
end

always @(posedge clk_s or posedge clr)
begin
if(clr == 1)
begin
state <= s0;
count <= 0;
timedis1 <= 0;
timedis2 <= 0;
end
else
begin
if(allred == 1)
begin
state <= s5;
count <= 0;
end
else
begin
if(allyellow == 1)
begin
state <= s6;
count <= 0;
end
else
begin
case(state)
s0:if(count < time_g)
begin
state <= s0;
count <= count+1;
end
else
begin
state <= s1;
count <= 0;
timedis1 <= time_y;
end
s1:if(count < time_y)
begin
state <= s1;
count <= count+1;
end
else
begin
state <= s2;
count <= 0;
timedis1 <= time_r;
end
s2:if(count < time_rr)
begin
state <= s2;
count <= count+1;
end
else
begin
state <= s3;
count <= 0;
timedis2 <= time_g;

end
s3:if(count < time_g)
begin
state <= s3;
count <= count+1;
end
else
begin
state <= s4;
count <= 0;

timedis2 <= time_y;
end
s4:if(count < time_y)
begin
state <= s4;
count <= count+1;
end
else
begin
state <= s5;
count <= 0;
timedis2 <= time_r;
end
s5:if(count < time_rr)
begin
state <= s5;
count <= count+1;
end
else
begin
state <= s0;
count <= 0;
timedis1 <= time_g;
end
s6:begin
state <= s0;
count <= 0;
timedis1 <= time_g;

end

default state <= s2;
endcase
end
end
end
end

always @(*)
case(state)
s0: lights = 6'b001100;
s1: lights = 6'b010100;
s2: lights = 6'b100100;
s3: lights = 6'b100001;
s4: lights = 6'b100010;
s5: lights = 6'b100100;

s6: lights = 6'b010010;

default lights = 6'b100100;
endcase
endmodule
是这段吗?

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